This page is meant to contain various resources on simultaneous multithreading. It was formerly titled hyperthreading resources because I felt Intel's trademark name was pretty catchy. After going through stacks of papers on SMT I felt it worthwhile to get them organized.

Over the years I have received many messages from those of you who found this page as well as its significantly larger sister page useful. Nearing the completion of my graduate program, I have decided to discontinue with updates as of January 2007. Your encouragement throughout has been greatly appreciated.

Slides from Intel Developer Forum 2001. Click either image for an enlarged view.

News articles are listed in chronological order. All other links are arranged in a somewhat less organized way. Documents relating to both SMT and CMP are included both here and on the CMP page.

All links point to PDF or HTML, except for the source code archives. To the best of my knowledge, all materials presented here were obtained legally and are freely available on the web if used for non-profit purposes.

Press releases

• August 29, 2001. Intel Xeon processors already employ Hyperthreading by Jack Robertson. CMP Media.
• December 10, 2001. Intel, Sun sketch multiprocessor chip plans by Rick Merritt. In an early article on hyperthreading, Merritt mistakenly refers to SMT chips as 'multi-core architectures' that simplify validation work.
• January 10, 2002. HyperThreading implementation in Windows XP by Rick C. Hodgin. Geek.com. HyperThreading presented somewhat of a challenge for Microsoft because the hardware abstraction layer (HAL) had to be extensively redesigned. The followup comments indicate confusion on how hyperthreading is meant to work under Windows XP.
• May 3, 2002. Microsoft warns Intel hyperthreading no panacea by Mike Magee. the Inquirer.
• October 3, 2002. Desktop Hyper-Threading - Coming Soon! by Nick Stam. ExtremeTech. An announcement at Intel Developer Forum revealed that hyperthreading would be available on desktops one year earlier than expected.
• October 10, 2002. Intel hyperthreading shows Digital roots by Michael Kanellos. CNET News.com. This article from 2002 recalls some of the history of SMT research.
• October 15, 2002. Intel Shows Multicore Itanium by Ashlee Vance. PC World. Confusion regarding multicore vs HyperThreading.
• November 13, 2002. Intel hopes new chip will spur sales by Michael Kanellos. CNET News.com. The triumphant release of the 3 GHz hyperthreaded Pentium 4. "It is just free performance," Paul Otellini said.
• February 4, 2003. IBM plots road ahead with Power5 (before SMT was announced) by Ashlee Vance. InfoWorld. Comments on Slashdot.
• April 8, 2003. Intel Offers Developers Hyperthreading Tool by Jeffrey Burt. eWeek.
• July 9, 2003. A Linux Mystery: Configuring for Virtual Processors by Vincent Ryan. NewsFactor. HyperThreading posed challenges for operating system designers.
• August 7, 2003. IBM's Power5+ to hit 3 GHz (POWER6) by Ashlee Vance. The Register.
• May 12, 2004. Sun to Test Niagara Chip by Robert McMillan. PC World.
• October 18, 2004. IBM 'stirs up the field' with P5 servers by Robert Jacques. vnunet.com. The Power5 cores would also support SMT.
• December 10, 2004. IBM's still got the Power (POWER5) by Steve Fox. InfoWorld.
• December 15, 2004. InfoWorld Thinks Apple Will Use IBM's Power5 Sometime in 2005 by Bryan Chaffin. the Mac Observer.
• February 3, 2005. Sun burnishes next-gen Sparc chips by Stephen Shankland. CNET News.com.
• April 20, 2005. Intel Pentium Extreme Edition 840 Processor Review by Ryan Shrout. PC Perspective. The 840 core also supports Hyper-Threading. Dual Cores Taken for a Spin in Multitasking Slashdot discussion.
• July 7, 2005. Forthcoming Dual-Core Intel Itanium Processor Achieves Fastest Four-Way Floating Point Benchmark (Montecito with HT). Intel Press.
• July 8, 2005. IBM introduces dual-core PowerPC 970 chip: But will Apple buy it? (POWER5) by Paul Hales. the Inquirer.
• July 18, 2005. Intel pulls rabbit out of Paxville 4MB dual core hat (dual-core HT) by Inquirer staff.
• August 15, 2005. Intel to Deliver Dual-Core, Hyper-Threaded Server Platforms Earlier Than Expected. Intel Press.
• November 14, 2005. McNealy Finally Takes Wraps Off "Niagara" Chip by Chris Kraeuter. Forbes.
• February 14, 2006. Sun Microsystems Announces Plans to Bring Breakthrough Efficiency of UltraSPARC T1 Processor to Upcoming Netra AdvancedTCA Blades and Carrier-Grade Rack Server Line (a.k.a. Niagara). Sun Press.
• April 18, 2006. AMD said to be researching 'reverse multi-threading' tech by Tony Smith. The Register. Comments on Slashdot.

Conference/journal papers

• Simultaneous Multithreading: Maximizing On-Chip Parallelism [abstract] by Dean M. Tullsen. Proc. ISCA-22, June 1995. The classic paper on SMT from 1995. Contains experiments demonstrating that SMT can outperform superscalar and chip multiprocessor architectures, as well as studies on optimal fetch policies.
• Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor by Dean Tullsen, Susan Eggers, Joel Emer, Henry Levy, Jack Lo and Rebecca Stamin. ISCA-23, June 1996. Now working together with Digital Equipment Corporation, they show that hyperthreading can be done by applying only a reasonable number of changes to a modern superscalar processor.
• Performance Analysis of Simultaneous Multithreading in a PowerPC-based Processor by F. Eskesen, M. Hack, T. Kimbrel, M. Squillante, R. Eickemeyer and S. Kunkel. WDDD '02. June 2002.
• Simultaneous Multithreading: A Platform for Next-Generation Processors by Susan Eggers, Joel Emer, Henry M. Levy, Jack Lo, Rebecca Stamm and Dean Tullsen. IEEE Micro, May 1997. The classic SMT journal paper.
• Multithreaded Processors by Theo Ungerer, Borut Robic and Jurij Silc. The Computer Journal, Volume 45, No. 3. November 2002. This journal paper presents a high-level historical view of multithreading.
• Hyper-Threading Technology. Intel Technology Journal, Volume 6, Issue 1. Contains 6 articles. Q1, 2001.
• HyperThreading Technology in the NetBurst Microarchitecture by David Koufaty and Deborah T. Marr. IEEE Micro, Volume 23, Issue 2. March 2003.
• How to Compare the Performance of Two SMT Microarchitectures by Yiannakis Sazeides and Toni Juan. ISPASS 2001, November 2001.
• Chip Multithreading: Opportunities and Challenges [slides] by Lawrence Spracklen and Santosh Abraham. HPCA-11. February 2005.
• Implicitly-Multithreaded Processors by Il Park, Babak Falsafi and T. N. Vijaykumar. ISCA-30, June 2003. See Shen & Lipasti's textbook for a good overview of implicitly multithreaded processors.
• Tuning Compiler Optimizations for Simultaneous Multithreading by Jack Lo, Susan Eggers, Hank Levy, Sujay Parekh and Dean Tullsen. MICRO-30. December 1997.
• Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor by Dean Tullsen, Jack Lo, Susan Eggers and Hank Levy. HPCA-5. January 1999.
• A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors [slides] by Ayose Falcon, Alex Ramirez and Mateo Valero. HPCA-11. February 2005.
• Improving Server Software Support for Simultaneous Multithreaded Processors [abstract] by Luke McDowell, Susan Eggers and Steven Gribble. Experiments on several software issues of SMT.
• A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies [homepage] [source] by Ronaldo Goncalves, Eduard Ayguade, Mateo Valero and Philippe Navaux.
• A Simultaneous Multithreading Simulator by Marc Torrant, Muhammad Shaaban, Roy Czernikowski and Ken Hsu. Computer Architecture News. Volume 27, Issue 5. December 1999.
• A Study of a Simultaneous Multithreaded Processor Implementation by Dominik Madon, Eduardo Sanchez and Stefan Monnier. Europar '99. August 1999. SSMT simulator maintained by Seungryul Choi.
• A Performance Comparison of DRAM Memory System Optimizations for SMT Processors by Zhichun Zhu and Zhao Zhang. HPCA-11. February 2005.
• Optimizing SMT Processors for High Single-Thread Performance by Gautham Dorai, Donald Yeung and Seungryul Choi. Journal of ILP, Volume 5. April 2003.
• Evaluation of Cache Assisted Multithreaded Architecture by Robert Rinker, Roopesh Tamma and Walid Najjar. MTEAC-1. January 1998.
• Dynamic Cache Partioning for Simultaneous Multithreading Systems by G. Edward Suh, Larry Rudolph and Srinivas Devadas. MIT LCS Computation Structures Group Memo-438. February 2001.
• Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading by Jack Lo, Susan Eggers, Joel Emer, Henry Levy, Rebecca Stamm and Dean Tullsen. ACM Transactions on Computer Systems, Volume 15, Issue 3. August 1997. One of the first and few papers to evaluate SMT with dependent threads.
• Mini-threads: Increasing TLP on Small-Scale SMT Processors by Joshua Redstone, Susan Eggers and Henry Levy.
• Front-End Policies for Improved Issue Efficiency in SMT Processors by Ali El-Moursy and David Albonesi. HPCA-9, February 2003.
• A Complexity-Effective Simultaneous Multithreading Architecture by Carmelo Acosta, Ayose Falcon, Alex Ramirez and Mateo Valero. ICPP '05. June 2005.
• Fetch Unit Design for Scalable Simultaneous Multithreading (ScSMT) by Juan Moure, Dolores Rexachs and Emilio Luque. Journal of Computer Science & Technology. 2001.
• SMT Fetch Bottleneck with Multiple Block Fetch by James Burns and Jean-Luc Gaudiot. MTEAC-4. December 2000.
• Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures by H. Pradeep Rao, S. K. Nandy and M. N. V. Satya Kiran. APCC '03. September 2003.
• Multithreading Decoupled Architectures for Complexity-Effective General Purpose Computing by Michael Sung, Ronny Krashinsky and Krste Asanovic. MEDEA '01. September 2001.
• Handling Long-latency Loads in a Simultaneous Multithreading Processor by Dean Tullsen and Jeffery Brown. What they found in this paper has proven to be very useful for our group because it classifies the behavior of popular SPEC benchmarks when run in various SMT combinations.
• Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors by Francisco Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. International Journal of High Performance Computing and Networking. April 2004.
• Power-Sensitive Multithreaded Architecture by John Seng, Dean Tullsen and George Cai.
• Understanding the Energy Efficiency of Simultaneous Multithreading [abstract] by Yingmin Li, Kevin Skadron, David Brooks and Zhigang Hu.
• Quantifying the SMT Layout Overhead - Does SMT Pull Its Weight? by James Burns and Jean-Luc Gaudiot. HPCA-6, January 2000. They attempt to take into account the various layout penalties of SMT.
• SMT Layout Overhead and Scalability by James Burns and Jean-Luc Gaudiot. IEEE Transactions on Parallel and Distributed Systems, February 2002.
• Thread-Sensitive Instruction Issue for SMT Processors by Behnam Robatmili, Nasser Yazdani, Somayeh Sardashti and Mehrdad Nourani. Computer Architecture Letters, Volume 3. August 2004.
• Thread-Sensitive Scheduling for SMT Processors by Sujay Parekh, Susan Eggers, Henry Levy and Jack Lo. University of Washington Technical Report 2000-04-02. April 2000.
• Efficient Instruction Schedulers for SMT Processors by Joseph Sharkey and Dmitry Ponomarev. HPCA-12. February 2006.
• Symbiotic Jobscheduling for a Simultaneous Multithreading Processor by Allan Snavely and Dean Tullsen. ASPLOS-IX. November 2000.
• Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor by Allan Snavely, Dean Tullsen and Geoff Voelker. SIGMETRICS '02. June 2002.
• Soft Real-Time Scheduling on Simultaneous Multithreaded Processors [slides] by Rohit Jain, Chris Hughes and Sarita Adve.
• The Need for Adaptive Dynamic Thread Scheduling in Simultaneous Multithreading by Chulho Shin, Seong-won Lee, and Jean-Luc Gaudiot. SPDSEC Workshop. September 2002.
• The Need for Adaptive Dynamic Thread Scheduling in Simultaneous Multithreading by Chulho Shin, Seong-Won Lee, and Jean-Luc Gaudiot. Parallel Processing Letters. Volume 14, No. 3 & 4. September & December 2004.
• Dynamic Scheduling issues in SMT Architectures by Chulho Shin, Seong-Won Lee and Jean-Luc Gaudiot. IPDPS-17. April 2003.
• Architectural Support for Enhanced SMT Job Scheduling by Alex Settle, Joshua Kihm and Andrew Janiszewski. PACT 2004. September 2004.
• Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors by Matthew DeVuyst, Rakesh Kumar and Dean Tullsen. IIPDPS '06. April 2006.
• Predictable Performance in SMT Processors by Francisco Cazorla, Peter Knijnenburg and Rizos Sakellariou. Computing Frontiers. April 2004.
• Microarchitectural Denial of Service: Ensuring Microarchitectural Fairness by Soraya Ghiasi and Dirk Grunwald. MICRO-35. November 2002.
• An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors by Steve Swanson, Luke McDowell, Michael Swift, Susan Eggers and Hank Levy. They claim that SMT enhances the effectiveness of speculative execution.
• Speculation-Aware Thread Scheduling for Simultaneous Multithreading by Dongsoo Kang and Jean-Luc Gaudiot. IEE Electronics Letters. Volume 40, No. 5, March 2004.
• Multithreaded Value Prediction by Nathan Tuck and Dean Tullsen. HPCA-11. February 2005.
• The Impact of Resource Partitioning on SMT Processors by Steven Raasch and Steven Reinhardt.
• Functional Unit Usage Based Thread Selection in a Simultaneous Multithreaded Processor by Deepak Babu, Lakshmi Bairavasundaram, Madhu Govindan and Ranjani Parthasarathi. HiPC 2001. 2001.
• Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance [slides] by Gautham Dorai and Donald Yeung. PACT-2002. September 2002.
• Approaching a Smart Sharing of Resources in SMT Processors by F.J. Cazorla, E. Fernandez, A. Ramirez and M. Valero. WCED-5. June 2004.
• Implicit vs. Explicit Resource Allocation in SMT Processors by Francisco Cazorla, Peter Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. DSD '04. September 2004.
• Dynamically Controlled Resource Allocation in SMT Processors by Francisco Cazorla, Alex Ramirez, Mateo Valero and Enrique Fernandez. MICRO-37. November 2004.
• QoS for High-Performance SMT Processors in Embedded Systems by Francisco Cazorla, Alex Ramirez, Mateo Valero, Peter Knijnenburg, Rizos Sakellariou and Enrique Fernandez. IEEE Micro. Volume 24, Issue 4. July-August 2004.
• Learning-Based SMT Processor Resource Distribution via Hill-Climbing by Seungryul Choi and Donald Yeung. ISCA-33. June 2006.
• Wire delay is not a problem for SMT (in the near future) by Zeshan Chishti and T. N. Vijaykumar. ISCA-31. June 2004.
• SMTp: An Architecture for Next-generation Scalable Multi-threading by Mainak Chaudhuri and Mark Heinrich. ISCA-31 June 2004.
• Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy by Eric Tune, Rakesh Kumar, Dean Tullsen and Brad Calder. HPCA-11. February 2005.
• Balancing Throughput and Fairness in SMT Processors by Kun Luo, Jayanth Gummaraju and Manoj Franklin. ISPASS 2001. November 2001.
• Evaluating and Improving Performance of Multimedia Applications on Simultaneous Multi-threading by Yen-Kuang Chen, Eric Debes, Rainer Leinhart, Matthew Holliman and Minerva Yeung.
• Evaluating the Impact of Simultaneous Multithreading on Network Servers Using Real Hardware by Yaoping Ruan, Vivek Pai, Erich Nahum and John Tracey. SIGMETRICS '05. June 2005.
• Initial Observations of the Simultaneous Multithreading Pentium 4 Processor by Nathan Tuck and Dean Tullsen.
• Multiprogramming Performance of the Pentium 4 with Hyper-Threading by James Bulpin and Ian Pratt. WDDD-3. June 2004.
• Physical Experimentation with Prefetching Helper Threads on Intels Hyper-Threaded Processors by Dongkeun Kim, Steve Shih-wei Liao, Perry Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar and John Shen. CGO '04. March 2004.
• Helper Threads via Virtual Multithreading On An Experimental Itanium 2 Processor-based Platform by Perry Wang, Jamison Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir Yunus, Terry Sych and John Shen. ASPLOS-XI. October 2004. More of fly-weight context switching rather than SMT.
• An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors by Matthew Curtis-Maury, Xiaoning Ding, Christos Antonopoulos and Dimitrios Nikolopoulos. IWOMP '05. May 2005.
• Design and Implementation of the POWER5 Microprocessor by J. Clabes, J. Friedrich, M. Sweet, J. Dilullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill and S. Dodson. ISSCC 2004. February 2004.
• Design and Implementation of the POWER5 Microprocessor by J. Clabes, J. Friedrich, M. Sweet, J. Dilullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill and S. Dodson. DAC-41. June 2004.
• IBM POWER5 Chip: A Dual-Core Multithreaded Processor by Ron Kalla, Balaram Sinharoy and Joel Tendler. IEEE Micro. March/April 2004.
• POWER5 Tops on Bandwidth: IBM's Design Is Still Elegant, But Itanium Provides Competition by Kevin Krewell. Microprocessor Report. December 2003.
• Sun Weaves Multithreaded Future: Afara Acquisition Brings New Life to SPARC by Kevin Krewell. Microprocessor Report. April 2003.
• Niagara: A 32-way Multithreaded SPARC Processor by Poonacha Kongetira, Kathirgamar Aingaran and Kunle Olukotun. IEEE Micro. March 2005.
• Montecito: A Dual-Core, Dual-Thread Itanium Processor by Cameron McNairy and Rohit Bhatia. IEEE Micro. March/April 2005.
• Exploring Efficient SMT Branch Predictor Design by Matt Ramsay, Chris Feucht and Mikko Lipasti.
• Exploiting Speculative Thread-Level Parallelism on a SMT processor by Pedro Marcuello and Antonio Gonzalez.
• Boosting SMT Performance by Speculation Control by Kun Luo, Manjoj Franklin, Shubhendu Mukherjee and Andre Sezne. IPDPS 2001. April 2001.
• Maximizing TLP with Loop-Parallelization on SMT by Diego Puppin and Dean Tullsen.
• On Performance, Transistor Count and Chip Space Assessment of of Multimedia-enhanced Simultaneous Multithreaded Processors by Ulrich Sigmund, Marc Steinhaus and Theo Ungerer. Contains excellent three dimensional graphs that tackle the problem of die area estimation for SMT.
• Simultaneous Multithreading and Multimedia by Heiko Oehring, Ulrich Sigmund, and Theo Ungerer. MTEAC '99.
• Simultaneous Multithreading-Based Routers by Kemathat Vibhatavanij, Nian-Feng Tzeng and Angkul Kongmunvattana. ICPP '00. August 2000.
• A Co-Phase Matrix to Guide Simultaneous Multithreading Simulation by Michael Van Biesbrouck, Timothy Sherwood and Brad Calder. ISPASS-2004. March 2004.
• Clustered Speculative Multithreaded Processors by Pedro Marcuello and Antonio Gonzalez. ICS-13. June 1999.
• Clustered Microarchitecture Simultaneous Multithreading by Seong-Won Lee and Jean-Luc Gaudiot. Euro-Par 2003. August 2003.
• Conjoined-core Chip Multiprocessing (SMT-style sharing) by Rakesh Kumar, Norman Jouppi , and Dean Tullsen. MICRO-37. December 2004.
• Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads by Stefanos Kaxiras, Girjia Narlikar, Alan D. Berenbaum and Zhigang Hu. CASES 2001. November 2001.
• Comparing the Energy Efficiency of CMP and SMT Architectures for Multimedia Workloads by Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen and Eric Debes.
• Area and System Clock Effects on SMT/CMP Processors [slides] by James Burns and Jean-Luc Gaudiot.
• Effects of Pipeline Complexity on SMT/CMP Power-Performance Efficiency by Ben Lee and David Brooks. WCED-6. June 2005.
• Temperature-Aware Design Issues for SMT and CMP Architectures by James Donald and Margaret Martonosi. WCED-5. June 2004.
• Heat-and-Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System by Michael Powell, Mohamed Gomaa and T.N. Vijaykumar. ASPLOS-XI. October 2004.
• Performance, Energy, and Thermal Considerations for SMT and CMP Architectures [slides] by Yingmin Li, Kevin Skadron, Zhigang Hu and David Brooks. HPCA-11. February 2005.
• Heat Stroke: Power-Density-Based Denial of Service in SMT by Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar and Carla Brodley. HPCA-11. February 2005.
• Leveraging Simultaneous Multithreading for Adaptive Thermal Control by James Donald and Margaret Martonosi. TACS-2. June 2005.
• AR-SMT - A Microarchitectural Approach to Fault Tolerance in Microprocessors [slides] by Eric Rotenberg. FTCS-29. 1999.
• Transient Fault Detection via Simultaneous Multithreading by Steven Reinhardt and Shubhendu Mukherjee. ISCA-27. June 2000.
• Detailed Design and Evaluation of Redundant Multithreading Alternatives [slides] by Shubhendu Mukherjee, Michael Kontz and Steven Reinhardt. ISCA-29. June 2002.
• Opportunistic Transient-Fault Detection [slides] by Mohamed Gomma and T. N. Vijaykumar. ISCA-32. June 2005.
• An Effective Simultaneous Multithreaded Processor Front-End [abstract] by L. He and Z. Liu. ACST '04. November 2004.
• (An SMT paper in simplified Chinese) by Longbing Zhang and Lijiang He.

Slides

• Multithreading for Latency by John Shen.
• From Instruction Level To Thread Level Parallelism by John Shen. Microprocessor Research Forum. October 2002.
• ILP versus TLP on SMT by Nick Mitchell, Larry Carter, Jeanne Ferrante and Dean Tullsen.
• Multithreaded Processor Architecture MPA by S. Niar and M. Adda. Some of the slides are in French.
• Improving Thread-level Parallelism in Simultaneous Multithreaded Processors by Susan J. Eggers.
• Simultaneous Multithreading: Multiplying Alpha Performance by Joel Emer. Plans for implementing SMT into the Alpha EV8 which was later cancelled.
• The Alpha 21364 and 21464 Microprocessors: Continuing the Performance Lead Beyond Y2K by Shubu Mukherjee. ~1999.
• Soft Real-Time Scheduling on Simultaneous Multithreaded Processors by Rohit Jain, Chris Hughes and Sarita Adve. See the corresponding conference paper in the "Conference/journal papers" section above. I must say that this slideshow sure has a pretty design.
• Area and System Clock Effects on SMT/CMP Processors by James Burns and Jean-Luc Gaudiot. See the corresponding conference paper in the "Conference/journal papers" section above.
• Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance by Gautham Dorai and Donald Yeung. PACT-2002. September 2002. See the corresponding conference paper in the "Conference/journal papers" section above.
• Chip Multithreading: Opportunities and Challenges by Lawrence Spracklen and Santosh Abraham. See the corresponding conference paper in the "Conference/journal papers" section above.
• A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors by Ayose Falcon, Alex Ramirez and Mateo Valero. See the corresponding conference paper in the "Conference/journal papers" section above.
• Performance, Energy, and Thermal Considerations for SMT and CMP Architectures by Yingmin Li, Kevin Skadron, Zhigang Hu and David Brooks. See the corresponding conference paper in the "Conference/journal papers" section above.
• AR-SMT - A Microarchitectural Approach to Fault Tolerance in Microprocessors by Eric Rotenberg. See the corresponding conference paper in the "Conference/journal papers" section above.
• Opportunistic Transient-Fault Detection [PPT] by Mohamed Gomma and T. N. Vijaykumar. See the corresponding conference paper in the "Conference/journal papers" section above.
• Detailed Design and Evaluation of Redundant Multithreading Alternatives by Shubhendu Mukherjee, Michael Kontz and Steven Reinhardt. ISCA-29. June 2002.
• Simultaneous Multithreading Implementation in POWER5 (a.k.a. POWER5: IBM's Next Generation Power Microprocessor) by Ron Kalla and Balaram Sinharoy. Hot Chips 15. August 2003.
• A 32-way Multithreaded SPARC Processor by Poonacha Kongetira. Hot Chips 16. August 2004.
• Montecito - The Next Product in the Itanium Processor Family (dual-core HT) by Cameron McNairy and Rohit Bhatia. Hot Chips 16. August 2004.

Research group homepages

• Dean Tullsen's research interests
• Simultaneous Multithreading Project at the University of Washington
• MVPsim
• SSMT simulator

From the classroom

• Beyond ILP II: SMT and variants. Scribe notes (done by Ben Serebrin) for lecture #13 of ELE482 taught by Anamaya Sullery at Stanford University.
• Simultaneous Multithreading (SMT) in Theory and Practice by Christian Ricci. For E/C5593 at the University of Colorado.
• Multithreading in SMT Processors by Dmitriy Yevseyev, Huyen Pham and Tim Reinholt in ECE570 at Oregon State.
• Evaluating Throughput and Fairness of Thread Fetch Policies for SMT Processors [HTML] [project homepage] by Pratyusa Manadhata and Vyas Sekar. "Our results indicate that our Sliding Window Schemes achieve a good tradeoff between the fairness and throughput for most workloads, and it does so without degrading the performance significantly."
• Evaluating Branch Predictors on an SMT Processor by David Mulvihill and Matthew Allen.
• Using Trache Cache in SMT by Huaxia Xia. The project results here aren't too insightful since he didn't create any data for a non-SMT processor with a trace cache to compare against.
• Multithreaded Microprocessors: Simultaneous Multithreading vs. Single-Chip Multiprocessing by Roxanne Canosa.
• A comparison of three architectures: Superscalar, Simultaneous Multithreading CPUs and Single-Chip Multiprocessor by Nivea Garg. Project for a course at the University of Maryland. 36 pages.
• Multithreaded Architectures by Dan Connors. Lecture notes from E/C5593 at the University of Colorado.
• Niagara: a 32-way Multithreaded SPARC Processor presented by Bogdan Romanescu for ECE 259 at Duke.
• Advanced Topics in Pipelining - SMT and Single-Chip Multiprocessor by Priya Govindarajan. Lecture notes for CMPE 200 at San Jose State University.
• Superscalar Case Studies: Intel Pentium III, AMD Athlon, Intel Pentium 4; SMT vs. CMP, Piranha by Miroslav Velev. Colorful lecture notes for ECE 4100/6100 at Georgia Tech.
• A Comparative Study of SMT and CMP Multiprocessors by Rajat Dua and Bhushan Lokhande. project for EE8365. 42 pages long.
• Hardware Fault Tolerance Through Simultaneous Multithreading (part 2) by Jonathan Winter. For CS717 at Cornell University.

Other resources

• Simultaneous multithreading from Wikipedia.
• TLP and the Return of KISS by Chris Rijk. Ace's Hardware. January 30, 2004.
• TLP Design Decisions by Chris Rijk. Ace's Hardware. November 28, 2004.
• MTEAC-5 and MTEAC-6. Both workshops contain many multithreading papers not explicitly listed here.
• Intel's Hyper-Threading homepage.
• The Basics of Hyper-Threading: What is it? at PCStats.com.
• Exploring Hyper-threading Performance from 2CPU.com.
• How to enable or disable hyperthreading on your PC (from Dell forums).
• From Linuxquestions.com, some sort of answer for anyone interested in using hyperthreading on Linux.
• Alpha EV8 (Part 2): Simultaneous Multi-Threat by Paul DeMone. Real World Technologies.
• Architecting the Future: Dr. Marc Tremblay by Brian Neal. Ace's Hardware. March 24, 2003.
• Multiple Cores, Multiple Pipes, Multiple Threads - Do we have more Parallelism than we can handle? by David Kirk. Panel at Hot Chips 17.
• Sun Details UltraSPARC Roadmap by Brian Neal. Ace's Hardware. February 26, 2003.
• Sun's Multi-Core Plans by Brian Neal. Ace's Hardware. February 13, 2003.
• Niagara: A Torrent of Threads by Chris Rijk. Ace's Hardware. April 19, 2004.
• Sun Niagara Performance Demo (streaming media). from Network Computing '05 Q1.
• POWER6 and ECLipz. Ars Technica. January 7, 2006.
• Intel "Paxville" Dual Core Xeon on the ASUS PVL-D Intel E7520 (Hyper-Threaded). GamePC. October 19, 2005. Slashdot topic Intel Dual Core Xeon Benchmarked.
• Improving Application Efficiency Through Chip Multi-Threading by Nagendra Nagarajayya. developers.sun.com. March 10, 2005. Comments on Slashdot.
• Introduction to Multithreading, Superthreading and Hyperthreading at Ars Technica. October 3, 2002.
• OpenSPARC T1 Release 1.0 (Niagara RTL and tools). SunSource.net. March 21, 2006.

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