News, academic papers, and presentations on dual-core and multicore processors

All links point to PDF or HTML, except for the source code archives. To the best of my knowledge, all materials presented here were obtained legally and are freely available on the web if used for non-profit purposes.

Die photos of an IBM POWER4 dual-core processor and the Cell 8-core processor. Click either image for an enlarged view.

Documents relating to both SMT and CMP are included both here and on the SMT page.

Over the years I have received many messages from those of you who found this page and the SMT page useful. By now multicore processors are ubiquitous and I can no longer keep on watch for every new piece of multicore news that appears on a daily basis. If 2006 is to be remembered as the year of multicore, January 2007 seems like a good time to discontinue with maintenance of this page. I will keep it online and perhaps it may still be useful for some historical perspective on multicore processors. Your encouragement throughout my years in graduate school has been greatly appreciated.

Press releases

• August 4, 1999. IBM to unveil Power4 processor at Hot Chips by David Lammers. EETimes.
• November 27, 2000. Chip Multiprocessing by Alan Joch. ComputerWorld.
• May 18, 2001. IBM's Power4 chip will fight disease first by Ashlee Vance. CNN.
• April 30, 2002. IBM POWER4 wins best microprocessor award. IBM Press.
• July 4, 2002. The 64-bit saga POWER4 vs Itanium2 by Nebojsa Novakovic. the Inquirer. With quite a passionate writing style indeed.
• October 15, 2002. Intel Shows Multicore Itanium by Ashlee Vance. What this news article mistakenly refers to as hyperthreading later turns out to be chip multiprocessing.
• February 4, 2003. IBM plots road ahead with Power5 by Ashlee Vance. InfoWorld. Comments on Slashdot.
• August 7, 2003. IBM's Power5+ to hit 3 GHz (POWER6) by Ashlee Vance. The Register.
• August 27, 2003. IBM finds ally for supercomputer-on-a-chip (TRIPS). by Michael Kanellos. CNN.
• October 13, 2003. Sun, Fujitsu to Rev SPARC Chips by Jeffrey Burt. eWeek.
• September 2, 2003. Processor adapts to shifting loads (TRIPS) by David Lammers. EE Times.
• September 16, 2003. Intel commits to multi-core Pentiums, Xeons, Itanics by Tony Smith. The Register.
• December 17, 2003. Taming the Supercomputer by Michael Kanellos. CNET News.com interviews Tilak Agerwala to get some information on upcoming supercomputing projects such as Blue Gene L, PERCS and TRIPS.
• March 8, 2004. Sun Rolls Forward With Rock by Peter Glaskowsky. Microprocessor Watch #118. Microprocessor Report.
• May 3, 2004. Intel shoots for dual cores, wireless profits by John Spooner. CNET News.com. Following announcements regarding cancellation of Tejas and Jawhawk.
• May 12, 2004. Sun to Test Niagara Chip by Robert McMillan. PC World.
• May 16, 2004. Don't bet on dual core Prescotts, Intel says by Mike Magee. the Inquirer.
• May 18, 2004. Dual-core chips in 2005, says AMD by Tom Krazit. TechWorld.
• July 19, 2004. New server chips carry hidden cost by Jennifer Mears. NetworkWorldFusion. Comments on Slashdot.
• August 25, 2004. Dual-core chips bring dual caches by Michael Kanellos. CNET News.com.
• September 6, 2004. Intel, AMD Pack Dual Processing Cores on Single Chip by Mark Hachman. eWeek. Formerly titled 'Intel, AMD Double Down'.
• September 8, 2004. Intel Demonstrates New Chips - Multiple Functions Replace Speed as Main Feature by Jason Kelly and Ian King. Washington Post (subscription required).
• September 8, 2004. Intel Pushes Dual-Core Tech to Mainstream by Bob Keefe. NewsFactor.
• October 15, 2004. How Intel will rip up its current roadmaps by Charlie Demerjian. the Inquirer.
• October 18, 2004. IBM 'stirs up the field' with P5 servers by Robert Jacques. vnunet.com.
• October 19, 2004. Microsoft Reveals Licensing Plans for Dual-Core Chips by Peter Galli and Mark Hachman. eWeek. Comments on Slashdot.
• November 4, 2004. Intel claims edge over AMD on dual core chips by Derek Sooman. Techspot News.
• November 29, 2004. Details trickle out on Cell Processor by Brian Fuller and Ron Wilson. EETimes. Comments on Slashdot.
• November 29, 2004. Sony Discloses Details on Computer Chip. The Associated Press via ABC News.
• December 10, 2004. IBM's still got the Power (POWER5) by Steve Fox. InfoWorld.
• December 15, 2004. InfoWorld Thinks Apple Will Use IBM's Power5 Sometime in 2005 by Bryan Chaffin. the Mac Observer.
• December 15, 2004. Intel, HP part ways in Itanium 64-bit pact by Silicon Strategies. EETimes. Comments on Slashdot.
• December 17, 2004. Intel expands core concept for chips my Michael Kanellos. CNET News.com. Comments on Slashdot.
• January 29, 2005. The Consequence of Waking Up a Sleeping Giant: Intel Roadmaps Inside by Kristopher Kubicki. AnandTech. Comments on Slashdot.
• February 3, 2005. Sun burnishes next-gen Sparc chips by Stephen Shankland. CNET News.com.
• February 7, 2005. Intel details dual-core Itanium by Tony Smith. The Register.
• February 7, 2005. PS3 Power: Details on Cell by Chris Roper. IGN.
• February 8, 2005. CELL Processor Gets Ready to Entertain the Masses by Dave Bursky. Electronic Design.
• February 8, 2005. The Quest for More Processing Power, Part One: "Is the single core CPU doomed?" by Johan De Gelas. AnandTech. Comments on Slashdot.
• February 12, 2005. HP and Intel round on Oracle over dual-core licences by Matt Loney. ZDNet UK. Comments on Slashdot.
• February 23, 2005. AMD Demos Dual-Core Athlon 64 by Alexander Wolfe. InformationWeek. Comments on Slashdot.
• February 23, 2005. AMD's Dual-Core Strategy: A Change-Up? by Mark Hachman. ExtremeTech.
• March 1, 2005. Intel Expects 75% Of Its Processors To Be Dual-Core Next Year by Darrell Dunn. InformationWeek. Comments on Slashdot.
• March 1, 2005. Intel: 15 dual-core projects under way by Michael Kanellos. CNET News.com.
• March 3, 2005. AMD to release notebook dual-core simultaneously with desktop chip by Wolfgang Gruener. Tom's Hardware Guide. Comments on Slashdot.
• March 3, 2005. Intel banks on new architecture by John Dvorak. CBS MarketWatch.
• March 7, 2005. Sum is greater than the whole by Ed Sperling. Electronic News.
• April 12, 2005. Intel First to Ship Dual Core by Michael Singer. InternetNews. Comments on Slashdot.
• April 17, 2005. Dell XPS Gen 5 by Joel Santo Domingo. PC Magazine. A 2nd Core to Keep Windows Chugging Along? Slashdot discussion.
• April 20, 2005. Intel Pentium Extreme Edition 840 Processor Review by Ryan Shrout. PC Perspective. Dual Cores Taken for a Spin in Multitasking Slashdot discussion.
• April 20, 2005. Hands on with Production Dual-Core AMD Opteron. Firing Squad.
• April 20, 2005. AMD Dual-Core Opteron Performance Preview. Firing Squad. This article benchmarks the dual-core Opteron against the dual-core Pentium Extreme Edition. Comments on Slashdot.
• April 21, 2005. AMD Announces World's First 64-Bit, x86 Multi-Core Processors For Servers And WorkStations At Second-Anniversary Celebration of AMD Opteron Processor. AMD Press.
• April 26, 2005. AMD may deliver quad core processors by 2007 by Derek Sooman.
• May 5, 2005. The Dual-Core War: Is Intel in Trouble? by Gundeep Hora. CoolTechZone. Comments on Slashdot.
• May 26, 2005. Intel Pentium D dual-core desktop CPU by HEXUS.net. The Register.
• May 27, 2005. Intel launches new multicore Pentium D. Sci-Tech Today.
• June 1, 2005. AMD edges Intel in early dual-core benchmarks by Michael Kanellos. CNET News.com.
• June 2, 2005. Intel's dual-core notebook chip knows how to share by Tom Krazit. Infoworld.
• June 13, 2005. Steve Jobs Not Impressed With the Cell Processor by Cesar A. Beradini. Team Xbox.
• July 7, 2005. Forthcoming Dual-Core Intel Itanium Processor Achieves Fastest Four-Way Floating Point Benchmark. Intel Press.
• July 8, 2005. IBM launches dual-core PowerPC 970 chip. LinuxDevices.com.
• July 8, 2005. IBM introduces dual-core PowerPC 970 chip: But will Apple buy it? by Paul Hales. the Inquirer.
• July 8, 2005. Intel tweaks Pentium D for servers by Michael Singer. CNET News.com.
• July 18, 2005. Intel pulls rabbit out of Paxville 4MB dual core hat by Inquirer staff.
• August 15, 2005. Intel to Deliver Dual-Core, Hyper-Threaded Server Platforms Earlier Than Expected. Intel Press.
• August 22, 2005. Tutorial: Build A Dual-Core System by Carol Ann Muff. InformationWeek.
• August 25, 2005. Intel looks to 'Dunnington' multi-core Xeon future by Tony Smith. The Register.
• September 2, 2005. Valve's Gabe Newell 'Steamed' Over Next-Gen. GameDaily.biz.
• October 25, 2005. Intel Changes CPU Road Map by Tom Krazit. PC World.
• October 25, 2005. Software limits multicore ICs, panelists say by Richard Goering. EETimes.
• September 9, 2005. Intel's 65nm Gameplan: Presler and Cedar Mill Updates by Kristopher Kubichi. AnandTech.
• November 14, 2005. McNealy Finally Takes Wraps Off "Niagara" Chip by Chris Kraeuter. Forbes.
• December 5, 2005. Codename cornucopia reveals Intel's 65nm CPU plans by Tony Smith. Reg Hardware.
• December 13, 2005. Sun pours Niagara II all over Great Lakes by Ashlee Vance. The Register.
• January 16, 2006. Intel Bests AMD With Core Duo by Darrell Dunn. InformationWeek.
• February 10, 2006. Intel shows off its quad core by Michael Kanellos. CNET News.com.
• February 11, 2006. Intel offers four-core trip to Clovertown by Ashlee Vance. The Register.
• February 14, 2006. Sun Microsystems Announces Plans to Bring Breakthrough Efficiency of UltraSPARC T1 Processor to Upcoming Netra AdvancedTCA Blades and Carrier-Grade Rack Server Line (a.k.a. Niagara). Sun Press.
• March 7, 2006. Spring IDF 2006 Conroe Preview: Intel Regains the Performance Crown by Anand Lal Shimpi. AnandTech. Comments on Slashdot.
• March 8, 2006. Sun has four-way UltraSPARC T1 box coming by Ashlee Vance. The Register.
• March 9, 2006. Intel Math: 2+2=Quad-Core Processor by Darrell Dunn. InformationWeek.
• March 14, 2006. Sun's Rock goes 16 cores and arrives with multi-core friends by Ashlee Vance. The Register.
• May 19, 2006. Intel's Core Duo meets the desktop by Tim Smalley. bit-tech.net. Comments on Slashdot.
• April 18, 2006. AMD said to be researching 'reverse multi-threading' tech by Tony Smith. The Register. Comments on Slashdot.
• June 4, 2006. Intel Conroe Performance Preview by Tim Smalley. Comments on Slashdot.
• June 9, 2006. Intel Core 2 Duo Peformance Update by Dave Altavilla and Marco Chiapetta. hothardware.com. Comments on Slashdot.
• June 26, 2006. Intel Introduces Xeon 5100 Server Chip by Dan Goodin. Washington Post.
• June 28, 2006. Microsoft ponders Windows successor (multicore) by Paul Krill. InfoWorld. Comments on Slashdot.
• July 14, 2006. Intel Conroe Core 2 Duo/Extreme Processors by Tarinder Sandhu. Hexus.net. Comments on Slashdot.
• July 14, 2006. Game Over? Core 2 Duo Knocks Out Athlon 64 by Patrick Schmid and Bert Topelt. Tom's Hardware Guide. Slashdot topic with comments and links to many related articles.
• July 24, 2006. Merom crashing Intel's Core 2 Duo launch event by Tom Krazit. CNET News.com. Comments on Slashdot.
• July 26, 2006. AMD Demos 4x4 Platform by Anush Yegyazarian. PC World.
• July 26, 2006. Intel Dual-Core FAQ by Eli Milchman. Wired News.
• July 27, 2006. Intel Calls Core 2 'Best In World', Slashes Prices 60% by Mark Hachman. PC World.
• August 22, 2006. Intel's Core 2 Under Linux by augustus. LinuxHardware.org. Comments on Slashdot.
• August 22, 2006. Sun confirms all about 64-thread Niagara II by Ashlee Vance. The Register.
• September 22, 2006. IBM's Power7 chip going into Opteron motherboards by Ashlee Vance. The Register.
• August 28, 2006. Intel Core 2 Duo 'Merom' Notebooks by Benny Har-Even. Comments on Slashdot.
• September 1, 2006. CPU core control key to power efficiency, says AMD by Wolfgang Gruener. TG Daily.
• September 26, 2006. Intel pledges 80 cores in five years by Tom Krazit. CNET News.com. Comments on Slashdot.
• September 27, 2006. IDF 2006: Terascale Processing Brings 80 Cores to your Desktop by Ryan Shrout. PC Perspective. Comments on Slashdot.
• September 27, 2006. Chip wars go to the Core by Tom Yager. InfoWorld. Comments on Slashdot.
• October 26, 2006. For AMD, more money means more problems by Tom Krazit. CNET News.com. Comments on Slashdot.
• September 29, 2006. Core 2 Extreme QX6700 Quad-Core Kentsfield Performance Preview. Hot Hardware. Comments on Slashdot.
• November 2, 2006. Intel's Core 2 Extreme QX6700 processor: Quad-core computing arrives on the desktop by Scott Wattson. The Tech Report. Comments on Slashdot.
• November 2, 2006. Sun's Niagara chip breaks like the Wind River by Ashlee Vance. The Register.
• November 3, 2006. Benchmarks: MacBook Pro gets its Core 2 Duo boost by James Galbraith. Macworld. Comments on Slashdot.
• November 8, 2006. Dell announces first quad-core servers by Colin Barker. ZDNet UK.
• November 14, 2006. Intel launches 'four brain' computer by Avi Krawitz. Jerusalem Post, and syndicated elsewhere.
• November 30, 2006. AMD Quad FX slaughtered by a single Intel CPU by George Ou. ZDNet.com.

Conference/journal papers

• The Case for a Single-Chip Multiprocessor by Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson and Kunyung Chang. ASPLOS-VII. October 1996.
• A Single-Chip Multiprocessor by Lance Hammond, Basem A. Nayfeh and Kunle Olukotun. IEEE Computer. Volume 30, No. 9. September 1997.
• Improving the Performance of Speculatively Parallel Applications by Kunle Olukoton, Lance Hammond and Mark Wiley. ICS '99. June 1999.
• Optimizing Compiler for a CELL Processor by A. Eichenberger, K. O'Brien, K. K. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao and M. Gschwind. PACT-2005. September 2005.
• Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation (abstract only) by Guri Sohi. keynote for MICRO-37. December 2004.
• Chip Multithreading: Opportunities and Challenges [slides] by Lawrence Spracklen and Santosh Abraham. HPCA-11. February 2005.
• The Jrpm System for Dynamically Parallelizing Java Programs by Michael K. Chen and Kunle Olukotun. This paper studies dynamically parallelizing applications on the Hydra processor, while earlier Hydra publications had seeked only to statically parallelize programs.
• The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization by J. Gregory Steffan and Todd Mowry. I'm including a classic thread-level data speculation paper here because the Hydra project's philosophy relies on TLDS.
• Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing by Luiz Andre Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets and Ben Verghese.
• Migration in Single Chip Multiprocessors by Kelly Shaw and Bill Dally. Computer Architecture Letters. Volume 1, No. 3. November 2002.
• Performance Implications of Single Thread Migration on a Chip Multi-Core by Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Demien Fetis and Andre Seznes. dasCMP '05 November 2005.
• Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores by Magnus Ekman and Per Stenstrom.
• Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors by Jian Li and Jose Martinez. P=AC². October 2004.
• Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors by Jian Li and Jose Martinez. ISPASS 2005. March 2005.
• Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors by Jian Li and Jose Martinez. HPCA-12. February 2006.
• Power-Performance Considerations of Computing on Chip Multiprocessors by Jian Li and Jose Martinez. Transactions on Architecture and Code Optimization. Volume 2, No. 4. December 2005.
• Optimizing Inter-processor Data Locality on Embedded Chip Multiprocessors by Guilin Chen and Mahmut Kandemir. EMSOFT '05 September 2005.
• Optimizing Array-Intensive Applications for On-Chip Multiprocessors by Ismail Kadayif, Mahmut Kandemir, Guilin Chen, Ozcan Ozturk, Mustafa Karakoy and Ugur Sezer. IEEE Transactions on Parallel and Distributed Systems. Volume 16, No. 5. May 2005.
• An Integer Linear Programming Based Approach for Parallelizing Applications in On-Chip Multiprocessors by Ismail Kadayif, Mahmut Kandemir and Ugur Sezer. DAC '02. June 2002.
• Optimizing Array-Intensive Applications for On-Chip Multiprocessors by Ismail Kadayif, Mahmut Kandemir, Guilin Chen, Ozcan Ozturk, Mustafa Karakoy and Ugur Sezer. IEEE Transactions on Parallel and Distributed Systems. May 2005.
• Temperature-sensitive Loop Parallelization for Chip Multiprocessors by Sri Hari Krishna Narayanan, Guilin Chen, Mahmut Kandemir and Yuan Xie. ICCD '05. November 2005.
• Fast Synchronization for Chip Multiprocessors by Jack Sampson, Ruben Gonzalez, Jean-Francois Collard, Norman Jouppi and Mike Schlansker. dasCMP '05 November 2005.
• Maximizing Area Efficiency for Single-Chip Server Processors by Jaehyuk Huh, Doug Burger and Stephen W. Keckler.
• Managing Wire Delay in Large CMP Caches [slides] by Bradford Beckman and David Wood. MICRO-37. December 2004.
• Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors by Michael Zhang and Krste Asanovic. ISCA-32. June 2005.
• Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors [slides] by Evan Speight, Hazim Shafi, Lixin Zhang and Ram Rajamony. ISCA-32. June 2005.
• Code Restructuring for Improving Cache Performance of MPSoCs by Guilin Chen and Mahmut Kandemir. ICCAD '05. November 2005.
• Cooperative Caching for Chip Multiprocessors by Jichuan Chang and Guri Sohi. ISCA-33. June 2006.
• A Case for Shared Instruction Cache on Chip Multiprocessors running OLTP by Partha Kundu, Murali Annavaram, Trung Diep and John Shen. MEDEA-Workshop '03. June 2004.
• Optimizing Replication, Communication, and Capacity Allocation in CMPs [slides] by Zeshan Chishti, Michael Powell and T. N. Vijaykumar. ISCA-32. June 2005.
• Interconnections in Multi-core Architectures Understanding Mechanisms, Overheads and Scaling [slides] by Rakesh Kumar, Victor Zyuban and Dean Tullsen. ISCA-32. June 2005.
• Interconnect-Aware Coherence Protocols for Chip Multiprocessors by Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev BAlasubramonian and John Carter. ISCA-33. June 2006.
• A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors by Matthew Farrens, Gary Tyson and Andrew Pleszkun.
• The RASE (Rapid, Accurate Simulation Environment) for Chip Multiprocessors by John D. Davis, Cong Fu and James Laudon. dasCMP '05. November 2005.
• Exploring the Cache Design Space for Large Scale CMPs by Lisa Hsu, Ravi Iyer, Srihari Makineni, Steve Reinhardt and Donald Newell. dasCMP '05. November 2005.
• A Chip Prototyping Substrate: The Flexible Architecture for Simulation and Testing (FAST) by John D. Davis, Stephen E. Richardson and Kunle Olukotun. dasCMP '05. November 2005.
• Chip Multi-Processor Scalability for Single-Threaded Applications by Neil Vachharajani, Matt Iyer, Chinmay Ashok, Manish Vahharajani, David August and Dan Connors. dasCMP '05. November 2005.
• Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors by Tomer Morad, Uri Weiser, AVnoam Kolodny, Mateo Valero and Eduard Ayguade. Computer Architecture Letters. July 2005.
• Fair Cache Sharing and Partitioning on a Chip Multiprocessor Architecture by Seongbeom Kim, Dhruba Chandra and Yan Solihin. PACT-2004. October 2004.
• Predicting the Impact of Cache Contention on a Chip Multiprocessor Architecture by Dhruba Chandra, Fei Guo, Seongbeom Kim and Yan Solihin. P=AC². October 2004.
• Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture by Dhruba Chandra, Fei Guo, Seongbeom Kim and Yan Solihin. HPCA-11. February 2005.
• Multiple-Path Execution for Chip Multiprocessors by Matthew Chidester, Alan D. George and Matthew Radlinski.
• Improving Multiple-CMP Systems Using Token Coherence by Michael Marty, Jesse Bingham, Mark Hill, Alan Hu, Milo Martinand David Wood. HPCA-11. February 2005.
• System Level Methodology for Programming CMP based Multi-threaded Network Processor Architecture by Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler and Karam S. Chatha. VLSI 2005. May 2005.
• Multipath Execution on Chip Multiprocessors Enabled by Redundant Threads by Karthik Sundaramoorthy, Zach Purser and Eric Rotenberg.
• Speculative Precomputation on Chip Multiprocessors by Jeffery A. Brown, Hong Wang, George Chrysos, Perry H. Wang and John P. Shen.
• Data Speculation Support for a Chip Multiprocessor by Lance Hammond, Mark Willey and Kunle Olukotun. ASPLOS-VIII. October 1998.
• A Case for Increased Operating System Support in Chip Multi-Processors by David Nellans, Rajeev Balasubramonian and Erik Brunvand. P=AC². September 2005.
• Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications [slides] by Lawrence Spracklen, Yuan Chou and Santosh Abraham. HPCA-11. February 2005.
• Dynamically Configurable Shared CMP Helper Engines for Improved Performance by Anahita Shayesteh, Glenn Reinman, Norman Jouppi, Suleyman Sair and Tim Sherwood. dasCMP '05. November 2005.
• Helper Threads via Virtual Multithreading On An Experimental Itanium 2 Processor-based Platform by Perry Wang, Jamison Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir Yunus, Terry Sych and John Shen. ASPLOS-XI. October 2004.
• Managing Wire Delay in Large Chip-Multiprocessor Caches by Bradford Beckmann and David Wood. MICRO-37. December 2004.
• Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values by Chun Liu, Anand Sivasubramaniam and Mahmut Kandemir.
• Future Execution: A Hardware Technique for Prefetching in Chip Multiprocessors by Ilya Ganusov and Martin Burtscher. PACT-2005. September 2005.
• Evaluation of Snoop-Energy Reduction Techniques for Chip-Multiprocessors by Magnus Ekman, Fredrik Dahlgren and Per Stenström.
• Performance of On-Chip Multiprocessors for Vision Tasks by Y. Chung, K. Park, W. Hahn, N. Park and V. K. Prasanna.
• Impact of CMP Design on High-Performance Embedded Computing by Patrick Crowley, Mark A. Franklin, Jeremy Buhler and Roger D. Chamberlain. High Performance Embedded Computing Workshop. September 2006.
• Transient-Fault Recovery for Chip Multiprocessors by Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar and Irith Pomeranz. ISCA-30. June 2003.
• A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors by Huiyang Zhou. Computer Architecture Letters. Volume 4. September 2005.
• POWER4 System Design for High Reliability by Douglas Bossen, Joel Tendler and Kevin Reick. IEEE Micro. March 2002.
• BulletProof: A Defect-Tolerant CMP Switch Architecture by Kypros Constantinides, Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin and Michael Orshansky. HPCA-12. February 2006.
• Energy-Efficient Thread-Level Speculation by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck and Josep Torellas. IEEE Micro. January/February 2005.
• Energy-aware Computation Duplication for Improving Reliability in Embedded Chip Multiprocessors by Guilin Chen, Mahmut Kandemir and Feihui Li. ASPDAC '06. January 2006.
• An Integrated Framework for Dependable and Revivable Architecture Using Multicore Processors by Weidong Shi, Hsien-Hsin Lee, Laura Falk and Mrinmoy Ghosh. ISCA-33. June 2006.
• Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures by Rakesh Kumar, Keith Farkas, Norman Jouppiy, Partha Ranganathany and Dean Tullsen.
• Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance by Rakesh Kumar, Dean Tullsen, Partha Ranganathan, Norman Jouppi and Keith Farkas. ISCA-31. June 2004.
• Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors by JoAnn Paul, Donald Thomas and Alex Bobrek. CODES 2004. October 2004.
• Scenario-Oriented Design for Single Chip Heterogeneous Multiprocessors by JoAnn Paul. IPDPS '05 Workshop 10. April 2005.
• Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors by B. H. Meyer, J. J. Pieper, JoAnn Paul, J. Nelson, S. Pieper, A. Rowe. IEEE Transactions on Computers. Volume 54, Issue 6. June 2005.
• An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget by Canturk Isci, Alper Buyutosunoglu, Chen-Yong Cher, Pradip Bose and Margaret Martonosi. MICRO-39. December 2006.
• An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation by James Donald and Margaret Martonosi. Computer Architecture Letters. Volume 5, No. 2. August 2006.
• ACCMP - Asymmetric Cluster Chip Multi-Processing by Tomer Morad, Uri Weiser and Avnoam Kolody. CCIT Technical Report #488. June 2004.
• Heterogeneous Chip Multiprocessors by Rakesh Kumar, Dean Tullsen, Norman Jouppi and Partha Ranganathan. IEEE Computer. November 2005.
• Conjoined-core Chip Multiprocessing by Rakesh Kumar, Norman Jouppi , and Dean Tullsen. MICRO-37. December 2004.
• Extending OpenMP for Heterogeneous Chip Multiprocessors by Feng Liu and Vipin Chaudhary. ICPP-2003. October 2003.
• An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors by Matthew Curtis-Maury, Xiaoning Ding, Christos Antonopoulos and Dimitrios Nikolopoulos. IWOMP '05. May 2005.
• Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture by Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen Kreckler and Charles Moore. ISCA-30. June 2003.
• Scaling to the End of Silicon with EDGE Architectures by D. Burger, S. Keckler, K. McKinley, M. Dahlin, L. John, C. Lin, C. Moore, J. Burrill., R. McDonald, W. Yoder and the TRIPS team. IEEE Computer. Volume 37, No 7. July 2004.
• WaveScalar by Steven Swanson, Ken Michelson, Andrew Schwerin and Mark Oskin. MICRO-36. December 2003.
• Area-Performance Trade-offs in Tiled Dataflow Architectures by Steve Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen, Andrew Schwerin, Mark Oskin and Susan Eggers. ISCA-33. June 2006.
• Design and Implementation of the POWER5 Microprocessor (ISSCC) by J. Clabes, J. Friedrich, M. Sweet, J. Dilullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill and S. Dodson. ISSCC 2004. February 2004.
• Design and Implementation of the POWER5 Microprocessor (DAC) by J. Clabes, J. Friedrich, M. Sweet, J. Dilullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill and S. Dodson. DAC-41. June 2004.
• IBM POWER5 Chip: A Dual-Core Multithreaded Processor by Ron Kalla, Balaram Sinharoy and Joel Tendler. IEEE Micro. March/April 2004.
• POWER5 Tops on Bandwidth: IBM's Design Is Still Elegant, But Itanium Provides Competition by Kevin Krewell. Microprocessor Report. December 2003.
• UltraSPARC IV Mirrors Predecessor: Sun Builds Dual-Core Chip in 130mm. by Kevin Krewell. Microprocessor Report. November 2003.
• Sun Weaves Multithreaded Future: Afara Acquisition Brings New Life to SPARC by Kevin Krewell. Microprocessor Report. April 2003.
• Best of Servers of 2004: Where Multicore Is the Norm by Kevin Krewell. Microprocessor Report. January 2005.
• Niagara: A 32-way Multithreaded SPARC Processor by Poonacha Kongetira, Kathirgamar Aingaran and Kunle Olukotun. IEEE Micro. March 2005.
• Montecito: A Dual-Core, Dual-Thread Itanium Processor by Cameron McNairy and Rohit Bhatia. IEEE Micro. March/April 2005.
• CMP Implementation in Systems Based on the Intel Core Duo Processor by Avi Mendelson, Julius Mandelblat, Simcha Gochman, Anat Schemer, Rajshree Chabukswar, Erik Niemeyer and Arun Kumar. Intel Technology Journal. May 2006.
• Power Efficient Processor Architecture and The Cell Processor by H. Peter Hofstee. HPCA-11. February 2005.
• An Adaptive Chip-Multiprocessor Architecture for Future Mobile Terminals by Mladen Nikitovic and Mats Brorsson. CASES 2002. June 2002.
• Multiple Instruction Stream Processor by Richard Hankins, Gautham Chinya, Jamison Collins, Perry Wang, Ryan Rakvic, Hong Wang and John Shen. ISCA-33. June 2006.
• Design and Management of 3D Chip Multiprocessors using Network in-Memory by Feihui Li, Chrys Nicopoulos, Tom Richardson, Yuan Xie, Narayanan Vijaykrishnan and Mahmut Kandemir. ISCA-33. June 2006.
• A Multiprogrammed Workload Model for Energy and Performance Esimation of Adaptive Chip-Multiprocessors by Mladen Nikitovic and Mats Brorsson. IPDPS-18. April 2004.
• Hardware-Modulated Parallelism in Chip Multiprocessors by Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh and Margaret Martonosi. dasCMP '05. November 2005.
• Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor [slides] by John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie Jones IV, Diana Franklin, Venkatesh Akella and Fred Chong.
• Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams by by M. B. Taylor, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe and A. Agarwal.
• Scalar Operand Networks by Michael Taylor, Walter Lee, Saman Amarasinghe and Anant Agarwal. IEEE Transactions on Parallel and Distributed Systems. Volume 16, No. 2. February 2005.
• Area and System Clock Effects on SMT/CMP Processors by James Burns and Jean-Luc Gaudiot.
• Effects of Pipeline Complexity on SMT/CMP Power-Performance Efficiency by Ben Lee and David Brooks. WCED-6. June 2005.
• Maximizing CMP Throughput with Mediocre Cores by John D. Davis, James Laudon and Kunle Olukotun. PACT-2005. September 2005.
• Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window by Huiyang Zhou. PACT-2005. September 2005.
• Characterization of TCC on Chip Multiprocessors by Austen McDonald, Jaewoong Chung, Hassan Chafi, Chi Cao Minh, Brian Carlstrom, Lance Hammond, Christos Kozyrakis and Kunle Olukotun. PACT-2005. September 2005.
• Thermal-Effective Clustered Microarchitectures by Pedro Chaparro, Jose Gonzalez and Antonio Gonzalez. TACS-1. June 2004.
• Distributing the Frontend for Temperature Reduction by Pedro Chaparro, Grigorios Magklis, José González and Antonio González. HPCA-11. February 2005.
• Design Choices for Thermal Control in Dual-Core Processors by Soraya Ghiasi and Dirk Grunwald. WCED-5. June 2004.
• Thermal Management with Asymmetric Dual Core Designs by Soraya Ghiasi and Dirk Grunwald. University of Colorado Technical Report CU-CS-965-03. ~June 2004.
• Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads by Stefanos Kaxiras, Girjia Narlikar, Alan Berenbaum and Zhigang Hu. CASES 2001. November 2001.
• Comparing the Energy Efficiency of CMP and SMT Architectures for Multimedia Workloads by Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen and Eric Debes.
• Temperature-Aware Design Issues for SMT and CMP Architectures by James Donald and Margaret Martonosi. WCED-5. June 2004.
• Heat-and-Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System by Michael Powell, Mohamed Gomaa and T.N. Vijaykumar. ASPLOS-XI. October 2004.
• Techniques for Multicore Thermal Management: Characterization and New Exploration by James Donald and Margaret Martonosi. ISCA-33. June 2006.
• Thermal Modeling, Characterization and Management of On-Chip Networks by Li Shang, Li-Shiuan Peh, Amit Kumar and Niraj Jha. MICRO-37. December 2004.
• Performance, Energy, and Thermal Considerations for SMT and CMP Architectures [slides] by Yingmin Li, Kevin Skadron, Zhigang Hu and David Brooks. HPCA-11. February 2005.
• Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors by Matthew DeVuyst, Rakesh Kumar and Dean Tullsen. IIPDPS '06. April 2006.
• Locality-Conscious Workload Assignment for Array-Based Computations in MPSOC Architectures by Feihui Li and Mahmut Kandemir. DAC-42. June 2005.
• Mitigating Amdahl's Law Through EPI Throttling by Murali Annavaram, Ed Grochowski and John Shen. ISCA-32. June 2005.
• Fixing the Sequential Bottleneck by Regulating Energy Per Instruction on CMPs [html] by Murali Annavaram, Ed Grochowski and John Shen. Technology@Intel Magazine. October 2005.
• Impact of Parameter Variations on Multi-Core Chips by Eric Humenay, David Tarjan and Kevin Skadron. ASGI. June 2006.
• Power Efficiency for Variation-Tolerant Multicore Processors by James Donald and Margaret Martonosi. ISLPED. October 2006.

Patents

• Multiprocessor-type one-chip microcomputer with dual-mode functional terminals [freepatentsonline] [patentstorm.us] by Mitsuru Sugita, Mitsubishi Electric. Filed April 20, 1993. Issued April 9, 1996.
• Single chip multiprocessor architecture with internal task switching synchronization bus [freepatentsonline] [patentstorm.us] by Michael Rostoker and Douglas B. Boyle, LSI Logic. Filed May 3, 1996. Issued June 2, 1998.
• Parallel processor with redundancy of processor pairs [freepatentsonline] [patentstorm.us] by Antonio Esposito and Rosario Esposito. Filed May 30, 1996. Issued March 26, 2002.
• Shared floating-point unit in a single chip multiprocessor [freepatentsonline] [patentstorm.us] by Donald Steiss and Tuan Q. Dao, Texas Instruments. Filed May 15, 1997. Issued November 14, 2000.
• Single chip multiprocessor with shared execution units [freepatentsonline] [patentstorm.us] by David Meltzer, IBM. Filed June 6, 1997. Issued November 16, 1999.
• Chip multiprocessor with multiple operating systems [freepatentsonline] [patentstorm.us] by S. E. Richardson, G. Vondran, S. Siu, P. Keltcher, S. Venkataraman, P. Venkitakrishnan and J. Ku, Hewlett Packard. Filed May 29, 2001. Issued March 29, 2005.

Slides (from technical talks)

• CMP + TLS = The Future of Microprocessors by Kunle Olukotun.
• Area and System Clock Effects on SMT/CMP Processors by James Burns and Jean-Luc Gaudiot. See the corresponding conference paper in the "Conference/journal papers" section above.
• Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor by John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie Jones IV, Diana Franklin, Venkatesh Akella and Fred Chong. See the corresponding conference paper in the "Conference/journal papers" section above.
• Managing the Transition from Complexity to Elegance (POWER4, TRIPS) by Chuck Moore. keynote for WCED-4. June 2003.
• Managing Wire Delay in Large CMP Caches [PPT] by Bradford Beckman and David Wood. See the corresponding conference paper in the "Conference/journal papers" section above.
• Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors by Evan Speight, Hazim Shafi, Lixin Zhang and Ram Rajamony. See the corresponding conference paper in the "Conference/journal papers" section above.
• Optimizing Replication, Communication, and Capacity Allocation in CMPs by Zeshan Chishti, Michael Powell and T. N. Vijaykumar. See the corresponding conference paper in the "Conference/journal papers" section above.
• Interconnections in Multi-core Architectures Understanding Mechanisms, Overheads and Scaling [PPT] by Rakesh Kumar, Victor Zyuban and Dean Tullsen. See the corresponding conference paper in the "Conference/journal papers" section above.
• The Impact of Performance Asymmetry in Emerging Multicore Architectures by Saisanthosh Balakrishnan, Ravi Rajwar, Mike Upton and Konrad Lai. ISCA-32. June 2005.
• Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications by Lawrence Spracklen, Yuan Chou and Santosh Abraham. See the corresponding conference paper in the "Conference/journal papers" section above.
• Chip Multithreading: Opportunities and Challenges by Lawrence Spracklen and Santosh Abraham. See the corresponding conference paper in the "Conference/journal papers" section above.
• Performance, Energy, and Thermal Considerations for SMT and CMP Architectures by Yingmin Li, Kevin Skadron, Zhigang Hu and David Brooks. See the corresponding conference paper in the "Conference/journal papers" section above.
• A 32-way Multithreaded SPARC Processor by Poonacha Kongetira. Hot Chips 16. August 2004.
• Montecito - The Next Product in the Itanium Processor Family by Cameron McNairy and Rohit Bhatia. Hot Chips 16. August 2004.
• A Novel SIMD arch. for the CELL Heterogeneous Chip-Multiprocessor by Michael Gschwind, Peter Hofstee, Brian Flachs, Marty Hopkins, Yukio Watanabe and Takeshi Yamazaki. Hot Chips 17. August 2005.
• Programming and Performance Evaluation of the CELL Processor by Ryuji Sakai, Seiji Maeda, Christopher Crookes, Mitsuru Shimbayashi, Katsuhisa Yano, Tadashi Nakatani, Hirokuni Yano, Shigehiro Asano, Masaya Kato, Hiroshi Nozue, Tatsunori Kanai, Tomofumi Shimada and Koichi Awazu. Hot Chips 17. August 2005.
• Break Free: General-Purpose Multi-Core Architectures by Justin Rattner. keynote for PACT 2005. September 2005.

Research group homepages

• Hydra
• Smart Memories
• SynchroScalar
• Raw
• SCALE
• TRIPS
• WaveScalar

From the classroom

• Multiprocessors on a Chip by Leon Gu and Dipti Motiani. A presentation for CS 15-740 at CMU.
• Evaluating Speculative Cache Coherency on a Chip Multiprocessor by Michael Chang, Noah Deneau and Manik Ghadiok. Project for ELEC 526 at Rice University.
• Polymorphic Architectures I. Scribe notes done by Chi Ho Yue and Rohit Gupta for EE392C at Stanford University. Contains a one-page concise overview of TRIPS.
• Multithreaded Microprocessors: Simultaneous Multithreading vs. Single-Chip Multiprocessing by Roxanne Canosa.
• A comparison of three architectures: Superscalar, Simultaneous Multithreading CPUs and Single-Chip Multiprocessor [homepage (down)] by Nivea Garg. Project for a course at the University of Maryland. 36 pages.
• Multithreaded Architectures by Dan Connors. Lecture notes from E/C5593 at the University of Colorado.
• Advanced Topics in Pipelining - SMT and Single-Chip Multiprocessor by Priya Govindarajan. Lecture notes for CMPE 200 at San Jose State University.
• Superscalar Case Studies: Intel Pentium III, AMD Athlon, Intel Pentium 4; SMT vs. CMP, Piranha by Miroslav Velev. Colorful lecture notes for ECE 4100/6100 at Georgia Tech.
• Niagara: a 32-way Multithreaded SPARC Processor presented by Bogdan Romanescu for ECE 259 at Duke.
• PhD Thesis Proposal: System Design for a Chip Multiprocessor by Bin Ren. His proposal looks promising and very well thought-out. Examines CMP from OS perspectives.
• A Comparative Study of SMT and CMP Multiprocessors by Rajat Dua and Bhushan Lokhande. for EE8365. 42 pages.

Other resources

• Chip-level multiprocessing from Wikipedia.
• Multi-core (computing) from Wikipedia.
• Platform 2015: Intel Processor and Platform Evolution for the Next Decade by S. Borkar, P. Dubey, K. Kahn, D. Kuck, H. Mulder, S. Pawlowski and J. Rattner. August 2005.
• TLP and the Return of KISS by Chris Rijk. Ace's Hardware. January 30, 2004. Features specs and estimated release dates for Xeon, Itanium, POWER and SPARC products.
• TLP Design Decisions by Chris Rijk. Ace's Hardware. November 28, 2004
• Intel IXP2580 Network Processor. Update: Many successors to this IXP processor have been developed.
• Are Single-Chip Multiprocessors in Reach? A roundtable featuring commentary by Reinaldo Bergamaschi, Ivo Bolsens, Rajesh Gupta, Randolph Harr, Ahmed Jerraya, Kurt Keutzer, Kunle Olukotun and Kees Vissers. IEEE Design & Test of Computers, January-February 2001.
• A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect by M. Z. Urfianto, T. Isshiki, A. U. Khan, D. Li and H. Kunieda. D & R Industry Articles.
• POWER4 System Microarchitecture. Whitepaper from IBM.
• IBM POWER4 Processor Review by Pavel Danilov at digit-life.com.
• Power4 vs. Itanium 2: "Madison" Takes the Lead published by Cambridge Consulting. The report concludes that the Itanium 2 processor outclasses the Power4, although this study was probably funded by HP or Intel.
• Supporting ILP in tiled architectures: wasted effort, or a good idea?. Panel at ISCA 2004 featuring Fred Chong, Sriram Vajapeyam, Krste Asanovic, Doug Burger, Christos Kozyrakis and Anant Agarwal (host).
• Chip Multiprocessors are here, but where are the threads?. Panel at ISCA 2005 featuring Babak Falsafi (host), Maurice Herlihy, Wen-Mei Hwu, Todd Mowry, Gurindar Sohi, Marc Tremblay and Michael Wolfe.
• Multiple Cores, Multiple Pipes, Multiple Threads - Do we have more Parallelism than we can handle? by David Kirk. Panel at Hot Chips 17.
• Architecting the Future: Dr. Marc Tremblay by Brian Neal. Ace's Hardware. March 24, 2003.
• Sun Details UltraSPARC Roadmap by Brian Neal. Ace's Hardware. February 26, 2003.
• Sun's Multi-Core Plans by Brian Neal. Ace's Hardware. February 13, 2003.
• Niagara: A Torrent of Threads by Chris Rijk. Ace's Hardware. April 19, 2004.
• Sun Niagara Performance Demo (streaming media) from Network Computing '05 Q1.
• POWER6 and ECLipz. Ars Technica. January 7, 2006.
• A closer look at AMD's dual-core architecture. The Tech Report. Q2 2005.
• AMD Financial Analyst meeting presentation by Chuck Moore (mentions Partitioned PowerNow!). June 10, 2005.
• Cell (microprocessor) from Wikipedia.
• Intel Pentium D Product Information.
• Intel Multi-Core Server Resource Center.
• OpenSPARC T1 Release 1.0 (Niagara RTL and tools). SunSource.net. March 21, 2006.
• Intel Multi-Core Processing - Intel Software Network.
• AMD wins dual-core duel (marketing gimmick video).
• Intel "Paxville" Dual Core Xeon on the ASUS PVL-D Intel E7520. GamePC. October 19, 2005. Slashdot topic Intel Dual Core Xeon Benchmarked.
• Apple putting Merom in MacBooks and MacBook Pros next month. jkOnTheRun. August 11, 2006. Comments on Slashdot.
• Cmpware, Inc. Tools for configurable multiprocessing.
• Multiprocessor Report blog at cmpware.com.
• The Multicore Expo. March 2006. Santa Clara, California.

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